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FDS_6533_6534_004
71M6533/G/H and 71M6534/H Data Sheet
1.4.7
Timers and Counters
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured
for counter or timer operations.
In timer mode, the register is incremented every 12 MPU clock cycles. In counter mode, the register is
incremented when the falling edge is observed at the corresponding input signal T0 or T1 (T0 and T1 are
the timer gating inputs derived from certain DIO pins, see Section 1.5.7 Digital I/O ). Since it takes 2 machine
cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the clock frequency (CKMPU).
There are no restrictions on the duty cycle, however to ensure proper recognition of the 0 or 1 state, an
input should be stable for at least 1 machine cycle.
Four operating modes can be selected for Timer 0 and Timer 1, as shown in Table 20 and Table 21 . The
TMOD Register, shown in Table 22 , is used to select the appropriate mode. The timer/counter operation
is controlled by the TCON Register, which is shown in
Table 23 . Bits TR1 ( TCON[6] ) and TR0 ( TCON[4] ) in the TCON register start their associated timers when
set.
Table 20: Timers/Counters Mode Description
M1
0
0
1
1
M0
0
1
0
1
Mode
Mode 0
Mode 1
Mode 2
Mode 3
Function
13-bit Counter/Timer mode with 5 lower bits in the TL0 or TL1 register
and the remaining 8 bits in the TH0 or TH1 register (for Timer 0 and
Timer 1, respectively). The 3 high order bits of TL0 and TL1 are held
at zero.
16-bit Counter/Timer mode.
8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or
TH1 , while TL0 or TL1 is incremented every machine cycle. When
TL( x) overflows, a value from TH( x) is copied to TL (x) (where x is 0
for counter/timer 0 or 1 for counter/timer 1.
If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops.
If Timer 0 M1 and M0 bits are set to 1, Timer 0 acts as two independent
8-bit Timer/Counters.
In Mode 3, TL0 is affected by TR0 and gate control bits, and sets the TF0 flag on overflow, while
TH0 is affected by the TR1 bit, and the TF1 flag is set on overflow.
Table 21 specifies the combinations of operation modes allowed for Timer 0 and Timer 1.
Table 21: Allowed Timer/Counter Mode Combinations
Timer 1
Mode 0
Mode 1
Mode 2
Timer 0 - mode 0
Timer 0 - mode 1
Timer 0 - mode 2
Yes
Yes
Not allowed
Yes
Yes
Not allowed
Yes
Yes
Yes
Table 22: TMOD Register Bit Description (SFR 0x89)
Bit
Symbol
Function
Timer/Counter 1:
TMOD[7] Gate
If TMOD[7] is set, external input signal control is enabled for Counter 0.
external gate control. The TR1 bit in the TCON register (SFR 0x88) must
also be set in order for Counter 1 to increment.
With these settings Counter 1 is incremented on every falling edge of the
logic signal applied to one or more of the interrupt sources controlled by
the DI_RBP , DIO_R1 , … DIO_RXX registers.
TMOD[6]
Rev 2
C/T
Selects timer or counter operation. When set to 1, a counter operation is
performed. When cleared to 0, the corresponding register will function as a
29
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